Current computer processing systems operate on binary data wherein a logic 1 is represented by a high voltage level (approximately Vcc, typically 3.3 or 5V) and a logic 0 is represented by a low voltage level (approximately Vss, typically 0V or ground). Consequently, conventional random access memory cells, dynamic (DRAM) or static (SRAM) charge a cell capacitor to the high voltage level to store a logic 1 and discharge the capacitor to the low voltage level to store a logic 0. During a read in DRAM's, the voltage on the cell capacitor (which may have drifted due to leakage) is differentially sensed against a reference voltage set between Vcc and Vss and then, depending on the result, restored by latching to the full Vcc or Vss level. Data from the cell is similarly output to the periphery and ultimately outside the DRAM device itself by driving various input/output (I/O) lines to approximately Vcc or Vss.
One of the main thrusts of current DRAM development efforts is to provide for the storage of more bits per DRAM chip (storage capacity). One means for accomplishing this goal is to increase DRAM cell density (i.e., the number of cells per given chip area). This requires the development of advanced circuit design and fabrication techniques to pack smaller cells into denser arrays, which is a time consuming and expensive process. Further, as DRAM cells become smaller and the arrays more dense, device physics increasingly become a limiting factor in the pace of progress in the development of new DRAMs. In any event, the development of new high cell-density DRAMs may take years to advance the design from theory to a commercially viable product.
Proposals have been made to increase memory capacity (for both volatile memory, such as DRAM, and non-volatile memory such as flash memory) by storing multiple bits per cell. In one approach, more than the traditional two voltage levels can be impressed on the storage mechanism of a cell, with each voltage level representing a different data value. For example, assume that for a given cell, data can be stored as one of four allowed voltage levels. A voltage of 0V can then be used to represent a two bit logic word "00", a voltage of approximately 1V to represent a logic "01", a voltage of approximately 2V to represent a logic "10" and a voltage of approximately 3V to represent a logic"11". In this fashion, an MSB and an LSB can be stored in a single cell. The exact voltages and the number of voltage levels used vary from scheme to scheme.
The actual implementation of these multivalued memories presents a number of problems. For instance, Murotani et al. (1997 IEEE International Solid State Circuit Conference, Digest of Technical Papers, pp 74-75, 1997) have proposed a 4-level storage device in which both a most significant bit (MSB) and an least significant bit (LSB) can be stored in a single cell as a function of capacitor voltage. The MSB is detected by sensing the stored voltage against a reference voltage that is substantially one-half of Vcc. After sensing, the LSB is then sensed against one-half of Vcc of offset by approximately one-third Vcc. The sign of the offset, (+, -), depends on the MSB (1,0).
Obtaining an adequate sense signal disadvantageously requires that the storage capacitor has a large capacitance, which in turn implies a chip area occupied by the storage element or a use of a high dielectric constant material in constructing the capacitor, or possibly a combination of both.
Moreover, the sense scheme in the prior art requires a specific bitline structure to effect proper sense and restore operation. The bitline pairs are segmented into two sections. The sections are unequal with one section disadvantageously required to have a bitline capacitance twice that of the other bitline section.
A need has therefore arisen for new circuitry and methods for implementing multivalued storage. The problem of efficient use of chip area must be addressed. A reduction in the density of storage elements on a chip vitiates the advantage offered by multilevel storage. To this end, the task of minimizing the size and complexity of the necessary circuitry cannot be ignored.